Sustainable Future Semiconductor Industry by Innovative Technologies: Transforming Physical Challenges into Growth Opportunities

EECS Colloquium

Wednesday, December 13, 2023

430 Soda Hall (Wozniak Lounge)
4:00 – 5:00 pm

 Youtube Webinar

Abstract

In the last few years, we have witnessed an unprecedented amount of data being generated, processed, and stored for creating new values in our daily lives in the digital transformation (DX) era, opening a significantly high growth opportunity in the semiconductor industry. In order to satisfy such demanding market requirements while considering extremely smaller physical dimensions of silicon devices than 10 nm, however, there is an exciting and fruitful concern about how to achieve technical advancements in a profitable way. Thus, the key is cost-effectively improving PPA (power-performance-area) by relentless drive of technical innovations through ecosystem-wide and shared efforts. In this colloquium, I will present how we have satisfied the market’s requirements in the previous technology nodes and what challenges should be overcome for future technology nodes. Then, I will discuss promising innovative technology candidates including structures, materials, processes, and equipment for the next decades.

Biography

Daewon Ha received the B.S. and M.S. degrees in electrical engineering from Yonsei University, Seoul, Korea, in 1993 and 1995, respectively, and the Ph.D. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 2004. In 1995, he joined Samsung Electronics, Co., Ltd., Korea where he was involved in the development of world-first fully working 1 Gb and 512 Mb DRAM. From 2000 to 2004, he conducted research in the field of nanoscale CMOS devices using advanced transistor structures and materials such as UTBFET and FinFET. In 2004, he re-joined Samsung Electronics where he is now in charge of advanced device research lab including DRAM, Flash, Logic and emerging devices as a head of lab in semiconductor R&D center. He has published more than 50 technical papers and holds more than 80 issued and pending patents on memory technology. His current research interests are nanoscale CMOS devices, emerging memory technologies and reliability. He was a recipient of Best Paper Award from the European Solid-State Device Research Conference (ESSDERC) in 1999, and Samsung Best Paper Award (Gold Prize) in 2005. Dr. Ha served as an editor of IEEE EDL from 2012 to 2020, a sub-committee member of the International Electron Devices Meeting (IEDM) from 2010 to 2012, and the International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) from 2008 to 2010.