Current: Physical Electronics and Integrated Circuits

Program Requirements

All EECS MEng students should expect to complete four (4) technical courses within the EECS department at the graduate level, the Fung Institute's engineering leadership curriculum, as well as a capstone project that will be hosted by the EECS department. You must select a project from the list below.

2017-2018 Capstone Design Experience

IoT System-on-Chip (advisor Prof. Kristofer Pister)

Description - The Internet of Things System on Chip Design experience is a combination of an introductory class in analog (EE240A) or digital (EECS251A) design coupled with an advanced Capstone Project class in the Spring term. The Capstone Project class will focus on the design and implementation of a single-chip wireless sensor node for the Internet of Things. The chip will include a 32 bit RISC-V processor and memory, 2.4 GHz radio transceiver, energy scavenging interface, power management, on-board sensors, and sensor interfaces. Another exciting aspect of the class is that the goal is to submit the design for fabrication in 28nm or 45nm CMOS process at the end of the semester, which means that the students will get exposure working with realistic design kits and design flows.

One or more teams of students will divide the project into modules and work together to design and integrate the modules into a single chip. Topics include: Analog/RF mixed-signal, ASIC toolchain: layout, synthesis, extraction, verfication; design for test; matlab system modeling; interface design; floorplanning; system simulation.

2017-2018 Capstone Projects

For the capstone projects for Master of Engineering in Electrical Engineering and Computer Science (EECS) our department believes that the students are going to have a significantly better experience if the projects are followed closely by an EECS professor throughout the academic year. To ensure this, we have asked the faculty in each area for which the Master of Engineering is offered in our department to formulate one or more project ideas that the incoming students will have to choose from.

Project 1

TitleModern High-Speed Link Design (advisor Prof. Vladimir Stojanovic)

DescriptionThis project aims to create a design infrastructure for fast prototyping of high-speed serial interfaces for a variety of channel and modulation conditions (chip-to-chip, backplane, etc). The work will comprise creation of a library of standard building blocks for high-speed links (serializers, deserializers, transmit and receive equalizers, clock and data recovery, etc) for both PAM2 and PAM4 modulation formats. Building blocks will be designed at the behavioral modeling level (Verilog and Verilog A), mixed-signal and digital circuit and scripted layout level for accelerated design automation, targeting sub-65nm process nodes. We will target link designs in the 10-50Gb/s speed range. The project will sharpen the following design skills: system level and component modeling of high-speed links (timing, equalization, modulation); digital design of link back-ends in Verilog and synthesis, place and route flow; analog and mixed-signal design (DLL/PLL, driver and receiver circuits).

 

Project 2

Title - Silicon Photonics Design (advisor Prof. Vladimir Stojanovic & Prof. Ming Wu)

Description - This project aims at training students to develop design libraries for silicon photonic integrated circuits. The students will perform detailed electrical and optical simulations, and optimize the designs. They will also learn modern scripting methods to automate the physical design of the photonic devices and implement design rule and connectivity checks.

Project 3

Title - HD Processor Design (advisor Prof. Jan M. Rabaey)

Description - Computing with HD vectors, referred to as “hypervectors,” is a brain-inspired alternative to computing with numbers providing excellent energy-efficiency and error tolerance. This project aims to propose a general hardware architecture for HD-based classification tasks. The main goal is to design an efficient and reconfigurable HD encoder that can be reused across a set of cognitive tasks. The architecture should be described using synthesizable Verilog and tested toward an ASIC or FPGA design flow.

Project 4

Title - Tele Health (advisor Prof. Gerald Friedland)

Description - Students will support a CITRIS PCARI project together with UC Davis to build a device that measures infants' ability to hear for medical purposes. The device needs to work in the Phillipines and therefore needs to be adopted to local constraints, including sparse infrastructure, laws, and the educational situation of the medical professionals.

Project 5

Title - VR system for MRI (advisor Prof. Jack Gallant)

Description - The aim of this project is to construct input devices for use in the magnetic resonance imaging environment. MRI is currently the main tool for studying, modeling and decoding the human brain. The most sophisticated experiments involve VR, but VR is challenging in the MRI environment because of limitations in display and response devices. This project aims to design and build new display and optically-coupled response devices for use in the MRI scanner. 

Project 6

Title - On-chip Biosignal Computation for Health Monitoring (advisor Prof. Rikky Muller)

Description - Low-power wearable and implantable biosensors require energy efficient computation of biosignals for disease detection and health monitoring. This project aims to design and implement these low-power digital computations first on an FPGA and then in an ASIC digital synthesis flow. The student team will gain experience in digital design, implementation and test.

Project 7

Title - Ultra E-bike Design (advisor Prof. Seth Sanders)

Description - The team will design and build prototype ultra high performance e-bike(s). Will encompass assessment of state-of-art, then design of ultra-light hub and/or bottom bracket drive train. Technologies covered include battery system design, electric machine design, sensorless motor drive, crank torque and cadence sensing. Will aim to complete prototype during term. Ideal team will have 2 EE and 2 ME students.

Technical Courses

At least three of your four technical courses should be chosen from the list below. The remaining technical courses should be chosen from your own or another MEng area of concentration within the EECS Department.

Fall 2017

Spring 2018 (updated as of 10/20/17)

Note: The courses listed here are not guaranteed to be offered, and the course schedule may change without notice. Refer to the UC Berkeley Course Schedule for further enrollment information.