Prospective: Physical Electronics and Integrated Circuits

Program Requirements

All EECS MEng students should expect to complete four (4) technical courses within the EECS department at the graduate level, the Fung Institute's engineering leadership curriculum, as well as a capstone project that will be hosted by the EECS department. You must select a project from the list below.

2018-2019 Capstone Design Experience

IoT System-on-Chip (advisor Prof. Kristofer Pister)

Description - The Internet of Things System on Chip Design experience is a combination of an introductory class in analog (EE240A) or digital (EECS251A) design coupled with an advanced Capstone Project class in the Spring term. The Capstone Project class will focus on the design and implementation of a single-chip wireless sensor node for the Internet of Things. The chip will include a 32 bit RISC-V processor and memory, 2.4 GHz radio transceiver, energy scavenging interface, power management, on-board sensors, and sensor interfaces. Another exciting aspect of the class is that the goal is to submit the design for fabrication in 28nm or 45nm CMOS process at the end of the semester, which means that the students will get exposure working with realistic design kits and design flows.
One or more teams of students will divide the project into modules and work together to design and integrate the modules into a single chip. Topics include: Analog/RF mixed-signal, ASIC toolchain: layout, synthesis, extraction, verfication; design for test; matlab system modeling; interface design; floorplanning; system simulation.

2018-2019 Capstone Projects

For the capstone projects for Master of Engineering in Electrical Engineering and Computer Science (EECS) our department believes that the students are going to have a significantly better experience if the projects are followed closely by an EECS professor throughout the academic year. To ensure this, we have asked the faculty in each area for which the Master of Engineering is offered in our department to formulate one or more project ideas that the incoming students will have to choose from.

Project 1

TitleModern High-Speed Link Design (advisor Prof. Vladimir Stojanovic)

DescriptionThis project aims to create a design infrastructure for fast prototyping of high-speed serial interfaces for a variety of channel and modulation conditions (chip-to-chip, backplane, etc). The work will comprise creation of a library of standard building blocks for high-speed links (serializers, deserializers, transmit and receive equalizers, clock and data recovery, etc) for both PAM2 and PAM4 modulation formats. Building blocks will be designed at the behavioral modeling level (Verilog and Verilog A), mixed-signal and digital circuit and scripted layout level for accelerated design automation, targeting sub-65nm process nodes. We will target link designs in the 10-50Gb/s speed range. The project will sharpen the following design skills: system level and component modeling of high-speed links (timing, equalization, modulation); digital design of link back-ends in Verilog and synthesis, place and route flow; analog and mixed-signal design (DLL/PLL, driver and receiver circuits).

Project 2

Title - On-chip Biosignal Computation for Health Monitoring (advisor Prof. Rikky Muller)

Description - Low-power wearable and implantable biosensors require energy efficient computation of biosignals for disease detection and health monitoring. This project aims to design and implement these low-power digital computations first on an FPGA and then in an ASIC digital synthesis flow. The student team will gain experience in digital design, implementation and test.

Project 3

Title - Building a Software-Defined Radio (advisor Prof. Borivoje Nikolic)

Description - This project is looking for 3-4 teams that will design building blocks for a software-defined radio (SDR). The template for the project will be developped in the Fall'18 offering of the EE290C class. The building blocks will have added value by demonstrating a complete working radio prototype. Example building blocks include a carrier and symbol synchronization, FFT and equalization, universal error-correction decoder (for turbo, LDPC, polar codes), and interfaces to the processor system.

Project 4

Title - Design of High Performance Transceivers for Next Generation Wireless (5G++)  (advisor Prof. Ali Niknejad)

Description - Students will engage in the design of a next generation transceiver capable of 100 Gbps + datarates per spatial beam. Students will be teamed up with Ph.D. students and get hands-on design experience. The goal is to capture the designs in the Berkeley Analog Generator (BAG) Design Automation framework.

Technical Courses

At least three of your four technical courses should be chosen from the list below. The remaining technical courses should be chosen from your own or another MEng area of concentration within the EECS Department.

Fall 2017

Spring 2018 (tentative)

Note: The courses listed here are not guaranteed to be offered, and the course schedule may change without notice. Refer to the UC Berkeley Course Schedule for further enrollment information.